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dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
1/21 oki semiconductor msm6722 fedl6722-05 general description the msm6722 converts in real-time the pitch of the speech signal in a range of one octave upward or downward. two pitch control methods can be selected. one is to change the pitch in 17 steps by two switch inputs, and the other is to select one of 16 steps by four binary input lines. since a microphone preamplifier and a low-pass filter are built in, the pitch conversion set can easily be configured by connecting a microphone, amplifier, and speaker in the peripheral circuit. the msm6722 is functionally compared to the msm6322, as described below. 1. method of reseting the speech pitch step (up/dw mode) msm6322 prst pin only msm6722 .............. two methods are available. one is to reset by the prst pin only, and the other is to reset using the upc and dwc pins coneurrently. 2. change in pitch msm6322 speech pitch is changeable in 17 steps. dw up pitch step 8 pitch step 16 pitch step 0 msm6722 the pitch step does not change if a signal is input to the upc (dwc) pin when the pitch step is 16 or 0. up, dw pitch step 8 pitch step 16 pitch step 0 3. additional thr/ cha pin this pin outputs a voice signal without passing the pitch conversion circuit including adc?dac. oki semiconductor msm6722 pitch control ic for the speech signal fedl6722-05 issue date: feb. 27, 2002
2/21 oki semiconductor msm6722 fedl6722-05 features ? built-in microphone preamplifier ? built-in low-pass filters ? built-in 8-bit ad converter ? built-in 9-bit da converter ? speech pitch alterable in 17 steps (including the no pitch change step) ? master clock frequency at 4 mhz ? 5 v single power supply ? package : 24-pin plastic sop (sop24-p-430-1.27-k) (MSM6722GS-K) chip
3/21 oki semiconductor msm6722 fedl6722-05 block diagram C + min mout C + lin lout lpf fout sg sg adc adin voice changer circuit 8 dac 9 lpf dao C + aout timing & control pd (p3) upc (p2) dwc (p1) prst (p0) ms thr/ chg reset xt xt osc sg circuit sgc sg dv dd av dd dgnd agnd test pin configuration (top view) pd (p3) 1 upc (p2) 2 dwc (p1) 3 prst (p0) 4 ms 5 thr/ chg 6 test 7 dao 8 aout 9 adin 10 fout 11 av dd 12 24 23 22 21 20 19 18 17 16 15 14 13 dv dd xt xt reset dgnd sg agnd sgc min mout lin lout 24-pin plastic sop
4/21 oki semiconductor msm6722 fedl6722-05 pin descriptions common to up/down mode and binary mode 24 pin symboltype description 20 12 18 16 14 15 13 10 11 9 8 21 6 7 23 22 19 17 dv dd dgnd av dd agnd min lin mout lout adin fout aout dao reset thr/ chg test xt xt sg sgc i o i o o o i i i i o o digital power supply pin. insert a bypass capacitor of 0.1 m f or more between this pin and dgnd. digital ground pin. analog power supply pin. insert a bypass capacitor of 0.1 m f or more between this pin and agnd. analog ground pin. inverting input pins for the built-in op amplifier. the non-inverting input pin is connected internally to sg. mout and lout are output pins of the built-in op amplifier for min and lin respectively. input pin for the built-in 8-bit ad converter. output pin from the built-in lpf. connect to adin pin. output pin from built-in lpf. this pin is used to output speech signals and to connect the amplifier for driving speaker. output pin from built-in 9-bit da converter. the ic enters the initial state when this pin is at the "l" level. at this time, the oscillation stops and the da converter output (dao) and audio output (aout) fall to the gnd level. then the ic returns to the initial state. the ic has a built-in power-on-reset circuit. for normal power-on reset operation, supply the power within 1 msec. if power cannot be supplied within 1 msec, apply a reset pulse after the power is switched on. select pin for the pitch control or non-pitch control. with a "h" level input, the ic outputs a normal speech signal from the aout pin through the built-in op amplifier. with a "l" level input, the ic outputs a pitch controlled speech signal from the aout pin. test pin to be fixed to "l" level. crystal oscillator connecting pin. when using the external clock, use this pin as the input. crystal oscillator connecting pin. when using the external clock, this pin must be left open. these pins output the reference voltage (signal ground (sg)) of the analog circuit. the output is approximately 1/2 the av dd level.
5/21 oki semiconductor msm6722 fedl6722-05 up/down mode only 5 pin symboltype description 2 3 1 4 ms upc dwc pd prst i i i i mode select pin. this pin must always be tied low. pins for raising or lowering the pitch by one step at a time. the pitch changes by one step upward (or downward) each time a "h" level pulse is input to the upc (or dwc) pin. the circuit enters the "no pitch change" state when an "h" level pulse is input to these pins simultaneously. power-down pin. all clocks, including the internal oscillator circuit, are stopped when the pd pin is set to the "h" level. pitch reset pin. the circuit enters the "no pitch change" state when this pin is set to the "h" level. binary mode only 5 pin symboltype description 1 2 3 4 ms p3 p2 p1 p0 i i mode select pin. this pin must always be tied high. the pitch step is directly set by 4 pins (bits) of p3 (msb) to p0 (lsb). one of the 16 steps from step 0 (p3=p2=p1=p0="l") to step 15(p3=p2= p1=p0="h") can be set.
6/21 oki semiconductor msm6722 fedl6722-05 absolute maximum ratings power-supply voltage parameter condition rating unit input voltage storage temperature v dd v in t stg v v c ta = 25 c ta = 25 c symbol C0.3 to +7.0 C0.3 to v dd + 0.3 C55 to +150 recommended operating conditions power-supply voltage parameter condition range unit operating temperature master clock frequency v dd t op f osc v c mhz dgnd = agnd = 0 v symbol 4.5 to 5.5 C10 to +70 4 to 4.5 electrical characteristics dc characteristics "h" input voltage parameter v ih symbolcondition min typ max unit "l" input voltage "h" input current "h" input current "h" input current "l" input current "l" input current operating current consumption (1) operating current consumption (2) v il i ih1 i ih2 i ih3 i il1 i il2 i dd i pd v ih = v dd v ih = v dd v ih = v dd v il = gnd v il = gnd f osc = 4 mhz, no load at power down, no load 0.8 x v dd 20 C10 C20 6 0.2 x v dd 10 20 650 12 10 v v m a m a m a m a m a ma m a (ta = C10 to +70 c, dv dd = av dd = 4.5 v to 5.5 v, dgnd = agnd = 0 v) *1 *2 *4 *3 *2 at power down, no load 50 m a ta=C40 to +70 c ta=C40 to +85 c *1 applies to all input pins excluding the xt pin. *2 applies to the xt pin. *3 applies to all the input pins without pull-down resistors, excluding the xt pin (i.e., pins 1, 5-7, 10, 14, 16, 21; however pin 1 is applied only during up/down mode). *4 applies to the input pins with pull-down resistors, excluding the xt pin (i.e., pins 1, 2, 3, 4; however, pin 1 is applied only during binary mode).
7/21 oki semiconductor msm6722 fedl6722-05 analog characteristics da output relative error parameter | v dae | symbolcondition min typ max unit ad output relative error scf allowable input voltage range scf input impedance op amplifier open loop gain op amplifier input impedance op amplifier load resistance | v ade | v fin r fin g op r ina r outa no load no load f in = 0 to 4 khz 1 1 40 1 200 40 40 v dd C1 mv mv v m w db m w k w (ta = C10 to +70 c, dv dd = av dd = 4.5 v to 5.5 v, dgnd = agnd = 0 v) aout load resistance r aout 50k w ac characteristics dao output delay from falling edge of pd parameter t pdd symbolcondition min max unit pulse width of prst, upc, and dwc pulses time between upc and dwc pulses pitch change delay from rising edge of prst pitch change delay from rising edge of upc and dwc t udpw t rud t chg1 t chg2 f osc = 4 mhz f osc = 4 mhz f osc = 4 mhz f osc = 4 mhz f osc = 4 mhz 62 31 62 31 16 ms ms ms ms ms (ta = C10 to +70 c, f osc = 4 mhz, dv dd = av dd = 4.5 v to 5.5 v, dgnd = agnd = 0 v)
8/21 oki semiconductor msm6722 fedl6722-05 timing diagram pd(i) dao(o) t pdd 1/2 av dd prst(i) upc(i) dwc(i) t udpw t udpw t rud pitch change timing t chg1 t chg2 pitch step is 8 ("no pitch change" state) by prst raise/lower a pitch by one step (pitch steps 0 to 15)
9/21 oki semiconductor msm6722 fedl6722-05 functional description power supply wiring as shown in the diagram below, supply the power to this ic from the same power source, but separate the wiring for the analog and the logic sections. to improve the electrical characteristics, insert a bypass capacitor of 0.1 m f or more between dv dd and dgnd and between av dd and agnd. +5 v dv dd av dd dgnd agnd msm6722 do not supply the power to the analog section and the logic section from separate power sources; otherwise latch-up may occur. av dd dv dd analog power supply digital power supply no good +5 v av dd dv dd no good
10/21 oki semiconductor msm6722 fedl6722-05 connecting an oscillator connect ceramic or crystal oscillators to the xt and xt pins as shown below. the characteristics of recommended ceramic oscillators of murata mfg. and kyocera corporation are shown below for reference. c 2 c 1 xt xt msm6722 kyocera corporation murata mfg. optimal load capacity supply voltage range(v) operating temperature range( c) ceramic oscillator c 2 (pf) type maker cstls4m00g53-b0 (with capacitor) cstcr4m00g53-r0 (with capacitor) c 1 (pf) 4.5 to 5.5 C10 to +70 frequency (mhz) 4.0 33 kbr-4.0msa kbr-4.0mks pbrc4.00b 33 4.5 to 5.5 C10 to +70 4.0
11/21 oki semiconductor msm6722 fedl6722-05 min r2 v mo C + C + C + mout lin lout v in v lo r1 r3 r4 op amplifier 1 op amplifier 2 sg v dd v dd C1 1/2 v dd 1 gnd v lo v lo = r4 r2 ? r4 r3 r1 ? r3 v mo =v in (v) the output v lo of output amplifier 2 is connected to the input fin of the built-in lpf. the fin allowable input voltage (v fin ) ranges from 1 v to (v dd C1) v. therefore, the amplification ratio must be adjusted so that the v lo amplitude can be within the fin allowable input voltage range. for example, if v dd = 5 v, v lo becomes 3 v p-p max. if v lo exceeds the fin allowable input voltage range, the output of the lpf will be a clipped waveform. the load resistance r outa of the op amplifier is 200 k w or more. therefore, the feedback resistors r2 and r4 of the inverting amplifier circuit must be 200 k w or more. analog input amplifier circuit the msm6722 has two built-in operational amplifiers for amplifying the microphone output. each output amplifier is provided with an inverting input pin and output pin. the analog circuit reference voltage sg (signal ground) is connected internally to the non-inverting input of each output amplifier. for amplification, form an inverting amplifier circuit and adjust the amplifi- cation ratio by using external resistors, as shown below.
12/21 oki semiconductor msm6722 fedl6722-05 analog input amplifer circuit the output v lo of op amplifer 2 is connected to the input fin of the built-in lpf. the allowable fin input voltage v fin ranges from 1 v to (v dd C 1) v. therefore, the amplification factor must be adjusted so that the v fin amplitude can be within the allowable fin input voltage range. for example, if v dd = 5 v, v lo becomes 3 v pCp max. if v lo exceeds the allowable fin input voltage range, the output of the lpf will be a clipped waveform. the load resistance r outa of the op amplifier is 200 k w or more. therefore, the feedback resistors r2 and r4 must be 200 k w or more. when op amplifier 1 is not used and op amplifier 2 is used, the min pin must be connected to agnd or avdd, and the mout pin must be open. even if amplification is unnecessary, op amplifier 2 must be always used. below is an example of an analog input amplifier circuit when the amplification factor is 1. C + min mout agnd C + lin lout op amplifier 1 op amplifier 2 input signal (200k w ) r3 (200k w ) r4 sg msm6722
13/21 oki semiconductor msm6722 fedl6722-05 configuring sgc and sg pins the internal equivalent circuit around the sgc and sg pins is shown below. the sg signal is reference voltage (signal ground) for internal op amplifiers and lpf. install a capacitor between the sgc pin and agnd and between the sg pin and agnd respectively in order to make the sg signal noiseless. it is recommended to install an approx. 1 m capacitor, which should be determined after evaluating the tone quality. it takes several ten msec until the dc levels such as the sg level of the analog circuit is stabilized after the power-down mode is cancelled. the larger capacitance of a capacitor connected to sgc or sg requires the longer time for stabilizing. after the power-down mode is cancelled, enter voices after the dc levels for the analog circuit has been stabilized. when the device is in power-down mode, the output voltage of the sg pin becomes unstable. therefore, sg must not be supplied to external circuits. otherwise, power suppluy current may be leaked via the internal sg circuit. same is true for the sgc pin. + C agnd agnd agnd 20k w (typ) 50k w (typ) 50k w (typ) power-down signal switch is open during power-down mode sgc msm6722 av dd to op amplifier lpf sg
14/21 oki semiconductor msm6722 fedl6722-05 pitch-control circuit [binary mode] (p3, p2, p1, p0) as shown in the diagram below, this ic has an internal prevention circuit for approximately 62 ms of chattering . therefore, hold these pins at "h" level for 62 ms or more. p3, p2, p1, and p0 pins are used to directly set the pitch steps. sixteen pitch steps are provided, but step 16 cannot be set. [up/down mode] (upc, dwc, prst) as shown in the diagram below, this ic has an internal prevention circuit for approximately 62 ms of chattering . therefore, hold these pins at "h" level for 62 ms or more. p3 chattering prevention circuit p2 p1 p0 valid data to pitch register [binary mode] upc chattering prevention circuit dwc prst pulse input to pitch register [up/down mode] pitch-control circuit inputting a "h" level pulse to the upc pin raises the pitch by one step, and inputting a "h" level pulse to the dwc pin lowers the pitch by one step. inputting a "h" level pulse to the prst pin or to the upc and dwc pins at the same time sets the no-pitch change state (pitch step 8).
15/21 oki semiconductor msm6722 fedl6722-05 2 3 4 6 7 8 11 12 13 16 5 9 10 14 15 01 16 pitch step da sampling cycle ( s)/ frequency (khz) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 0 60/16.6 71/14.0 76/13.1 80/12.5 90/11.1 90/10.5 101/9.90 113/8.84 120/8.33 127/7.87 143/6.99 151/6.62 160/6.25 180/5.55 190/5.26 202/4.95 227/4.40 a pitch shifts in a range of about one octave upward or downward, centered at pitch step 8. the pitch shift is illustrated in the following keyboard diagram and the following table via corre- sponding frequencies. pitch conversion diagram pitch conversion table
16/21 oki semiconductor msm6722 fedl6722-05 application circuits up/down mode dv dd xt xt reset dgnd sg agnd sgc min mout lin lout pd (p3) upc (p2) dwc (p1) prst (p0) ms thr/ chg test dao aout adin fout av dd msm6722 0.1 m f 30 pf 30 pf 4.0 mhz 100 k w rst + 1 m f + 1 m f 51 pf 10 k w 100 k w + 0.47 m f 10 k w 330 k w 0.4 m f 51 pf up dw prst 0.1 m f sp speaker drive amplifier msc1157
17/21 oki semiconductor msm6722 fedl6722-05 binary mode dv dd xt xt reset dgnd sg agnd sgc min mout lin lout pd (p3) upc (p2) dwc (p1) prst (p0) ms thr/ chg test dao aout adin fout av dd msm6722 0.1 m f 30 pf 30 pf 4.0 mhz 100 k w rst + 1 m f + 1 m f 51 pf 10 k w 100 k w + 0.47 m f 10 k w 330 k w 0.4 m f 51 pf 0.1 m f sp speaker drive amplifier msc1157 hex switch
18/21 oki semiconductor msm6722 fedl6722-05 y x chip size chip thickness pad size chip substrate voltage pad no pad name x ( m m) y ( m m) 1 pd C1784 C602 2 upc C1784 C955 3 dwc C1784 C1310 4 prst C1314 C1391 5 ms C736 C1397 6 thr/ chg C275 C1397 7 test 53 C1397 8 dao 912 C1396 9 aout 1447 C1396 10 adin 1783 C974 11 fout 1783 C561 12 av dd 1733 C238 pad no pad name x ( m m) y ( m m) 13 lout 1782 356 14 lin 1782 780 15 mout 1782 1193 16 min 1351 1359 17 sgc 938 1359 18 agnd 598 1295 19 sg C127 1359 20 dgnd C650 1359 21 reset C1198 1359 22 xt C1787 1053 23 xt C1786 703 24 dv dd C1736 84 : 3.99 mm 3.08 mm : 350 m m 30 m m : 110 m m 110 m m : v dd 4 20 19 18 17 16 15 14 13 12 11 10 22 23 24 1 2 3 567 8 9 21 pad configuration pad layout (top view) view from the side cofiguring the pads pad coordinates (chip center is located at x=0 and y=0.)
19/21 oki semiconductor msm6722 fedl6722-05 (unit : mm) package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment package weight (g) oki electric industry co., ltd. rev. no./last revised epoxy resin 42 alloy solder plating ( 5 m m) 0.58 typ. 5/oct. 13, 1998 mirror finish sop24-p-430-1.27-k
20/21 oki semiconductor msm6722 fedl6722-05 revision history document no. date page 910 20 description fedl6722-04 fourth edition addition of revision history changed contents of the table for ceramic oscillators fedl6722-05 jul. 2001 feb. 27, 2002 previous edition current edition
21/21 oki semiconductor msm6722 fedl6722-05 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2002 oki electric industry co., ltd. printed in japan

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